In one type of conventional arrangement, a computer system includes a memory system. The memory system includes dual in-line memory modules (DIMM) that include dynamic random access memory (DRAM) devices. These DRAM devices typically are either 4 bits or 8 bits in width. The computer system also includes host processors that access the memory system. The host processors maintain local caches of data accessed in the memory system.
In this conventional arrangement, a fault in the memory system components may result in errors that may corrupt data written to or read from the memory system. In order to try to detect and/or correct such errors, the memory arrangement may implement error correction code (ECC) techniques. Also, in order to try to maintain data coherency of the local caches, the host processors employ a snoop message protocol.
In one such ECC technique, in each memory access, 8 ECC bits are associated with 64 data bits. Unfortunately, depending upon the particular configuration of the DIMM and width of the DRAM devices, the particular memory access modes that may be implementable in this conventional arrangement, consistent with and/or without reducing the arrangement's ECC capabilities, may be limited. Also, in this conventional arrangement, the snoop messages that may be sent between or among the host processors may consume undesirably large amounts of inter-processor processing and communication bandwidth. This may be especially true when such messages are communicated between or among processors that do not reside on the same processor die.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.